Magnetic memory and magnetic switch systems



Oct. 23, 1956 J. A. RAJCHMYAN ,7 ,3

MAGNETIC MEMORY AND MAGNETIC SWITCH SYSTEMS Filed Dec. 50, 1954 I 4Sheets-Sheet 1 OUTPUT .IN V EN TOR.

firm/mar Oct. 23, 1956 J. A. RAJCHMAN MAGNETIC MEMORY AND MAGNETICSWITCH SYSTEMS 4 Sheets-Sheet 5 Filed Dec. 50, 1954 m N m K m .0 w w m?y i Y Ma Q Kwm m \N v y TM. m E E Oct. 23, 1956 J. A. RAJCHMAN 2,768,367MAGNETIC MEMORY AND MAGNETIC SWITCH SYSTEMS Filed Dec. 30, 1954 4Sheets-Sheet 4 Patented MAGNETIC MEMORY AND MAGNETIC SWITCH SYSTEMS JanA. Rajchman, Princeton, N. J., assignor to Radio Corporation of America,a corporation .of Delaware Application December 30, 1954, Serial No.478,759

16 Claims. (Cl. 340-174) This invention relate to magnetic memorysystems, and also to improved switching means for such systems.

In an article by Jan A. Rajchman, in the Proceedings of the I. R. E.,for October 1953, entitled A' myriabit magnetic core matrix memory,there is described a memory system for storing information in arrays ofmagnetic cores. The array illustrated in the article is atwo-dimensional array of memory cores arranged in rows and columns. Thearray is driven by two, different magnetic matrix switches. Each switchcomprises an array of switch cores biased by a D. C. current. One switchis a column switch' and another switch is a row switch. Each switch coreof the column switch is linked to all the memory cores in one of thecolumns of the memory system by a column coil. Each switch core of therow switch is linked to the memory cores in one of the rows of thememory system by a row coil. A desired one of the memory cores is drivenby operating the row and column switches to excite the one row switchcore and the one column switch core which are coupled to the desiredmemory core. The switching program is symmetrical and comprises a first,positive pulse followed by a second, negative pulse. The two pulses areinduced in the one row and the one column coil which are respectivelycoupled to the excited switch cores. The amplitude of each pulse isregulated so as to generate one-half the magnetizing force required toturn over a memory core. The row and column coil currents risesimultaneously and are constant for a time at least equal to the switchtime of the memory cores. A binary one, arbitrarily represented by thestate P of a memory core, or a binary zero, arbitrarily represented bythe state N, can be written into the desired memory core by terminatingthe current pulses furnished by the driven switch cores at differenttimes, in the case of a binary one, and by terminating the currentpulses simultaneously, in the case of a binary zero. Other memorysystems employing asymmetrical current pulses comprising afull-amplitude, driving pulse of one polarity and a half-amplitude,inhibiting pulse of the other polarity are also known. In order toimprove the access time of the prior memory systems, a diiferentiatingresistance is placed in series with each of the respective column androw coils. The diiferentiating resistance aids the driving current in acoil in decaying rapidly to a zero value. Thus, the succeeding andopposite polarity current can be applied to the row and the column coilsthat much faster. The value of each of these resistances is made largewith respect to the value of the effective inductance of the memorycores which are coupled to the respective column and row coils.

In certain of the prior magnetic memory systems, the driving currentsare furnished by the selecting means. Because of the high coercive forceof the magnetic material and the desired short access time, a very highpower level is required. Thus, the selecting means are comprised ofvacuum tubes capable of producinghigh out- 2 put currents. In such case,the timing of the ditferent selecting means is diflicult because of thedesired short access time.

It is an object of the present invention to provide a more efiicientmemory system wherein improved access time is obtained using only theself-resistance of the respective coils.

Another object of the present invention is to provide an improved switchmeans for a memory system whereby the timing of different drivingcurrents is simplified.

Still another object of the present invention is to provide improvedmethods for writing information into and reading information out of amemory system.

Yet another object of the present invention is to provide an improvedselecting system using low power level selecting means.

A further object of the present invention is to provide improved meansfor and an improved method of operating a memory system.

According to the invention, a magnetic switch is comprised of aplurality of pairs of magnetic cores.

Each core of the respective core pairs is biased to one direction ofsaturation. A plurality of selecting windings, a drive winding, and anoutput winding are linked to each core. The drive windings are linked tothe respective cores of a pair in opposite senses, that is, one

winding is linked to one core of a pair in one sense and theotherwinding is linked to the other core of a pair in the oppositesense. The output windings of a core pair are also linked to therespective cores in opposite senses. The selecting windings are linkedto the respec-,

tive coresof a pairin the same sense. All the drive windings areserially connected and comprise a drive coil. The output windings of theindividual core pairs are serially connected and comprise a plurality ofdifferent output coils, one for each core pair. The selecting windingsof the core pairs are serially connected in combinatorial fashion andcomprise selecting coils. Each core pair has a different combination ofthe selecting coils linked thereto.

The switch is operated by selecting a desired combination of selectingcoils to drive one core pair substantially to the zero inductioncondition. Only a relatively low power is required for each selectingcoil because the selecting means do not furnish the currents for drivingthe memory cores. The flux changes caused by exciting the core pair tothe zero induction condition induce voltages in the output coil whichcancel each other due to the series opposition connection of the outputwindings. At some later time, a balanced drive pulse comprising a firstphase of one polarityand a second phase of the opposite polarity isapplied to the drive coil. The first phase drives one core of theselected pair from zero saturation towards positive saturation and theother core of the selected pair from zero saturation towards negativesaturation. The flux changes are opposite and induce aiding voltages ofone polarity in the output coil of the selected core pair. Similarly,the second phase of the drive pulse excites the two cores of theselected core pair and aiding voltages of the polarity opposite to theone polarity are induced in the output coil. Substantially no fluxchange is produced by the drive pulse in the nonselected core pairs.Therefore, practically no disturbing voltages are induced in thenon-selected output coils. The drive pulse is reproduced in the outputcoil of a selected pair without requiringa differentiating resistance.By applying a second drive pulse whose phases are opposite to the phasesof the first drive pulse, a simple program for Writing information intoand reading'information out of a memory can be achieved.

The present invention also includes other arrangements of the magneticswitch, and novel arrangements of a plurality of switches of the presentinvention for driving a magnetic memory.

The invention will be more fully understood, both as to its organizationand method of operation, from the following description when inconnection with the accompanying drawing in which like referencenumerals refer to similar parts, and wherein;

Fig. l is a schematic diagram of a core pair and windings thereof andillustrates the manner in which the windings are linked to the two coresof a core pair,

Fig. 2 is a schematic diagram of a core pair which adopts a conventionfor representing the cores and for representing the sense in which thevarious windings are linked to the cores,

Fig. 3 is a schematic drawing using the convention of Fig. 2 and is onearrangement of the core pairs to form a combinatorial switch,

Fig. 4 is a graph, somewhat idealized, of the hysteresis, loop of a corewhich is useful in explaining the operation of the invention,

Fig. 5 is a graph of waveforms which are useful in explaining theoperation of the memory systems of Figs. 6 and 8,

Fig. 6 is a schematic diagram of the arrangement of two magneticswitches according to the present invention in a two-dimensional memorysystem,

Fig. 7 is a detailed schematic drawing, using the convention of Fig. 2,of a core pair of one of the switches of the memory system of Fig. 6,and

Fig. 8 is a schematic arrangement of another memory system according tothe present invention.

Referring to Fig. l, the core pair 1 is comprised of a first core 3 anda second core 5. Each of the cores is comprised of a magnetic materialcharacterized by a substantially rectangular hysteresis loop. Certainferrite materials such as manganese-magnesium ferrite, and certainmetallic materials such as mopermalloy exhibit the desired hysteresischaracteristic. Each of the cores 3 and 5 has a bias winding 7, a pairof selecting windings 9, 11, a drive winding 13, and an output windinglinked thereto. The bias winding 7 of the core 3 is connected in seriesaiding relation to the bias winding 7 of the core 5 to form a bias coil17. By series aiding relation is meant that a current in a coil causes aflux change in the same direction both in the core 3 and in the core 5.The selecting windings '9 and 11 are connected in series aiding relationto the corresponding selecting winding 9 and 11 of the core 5 to formthe respective selecting coils 19 and 21. The drive winding 13 of thecore 3 is connected in series opposition to the drive winding 13 of thecore 5 to form a drive coil 23. By series opposition is meant that acurrent flowing in a coil induces a fiux change in one direction in onecore of the pair and a flux change in the opposite direction in theother core of the pair. Conversely, opposite directions of flux changesin the cores of a pair induce like polarity voltages in a seriesopposition connected coil. The output winding 15 of the core 3 isconnected in series opposition to the output winding 15 of the core 5 toform an output coil 25.

For the purpose of simplification of the drawing, the convention shownin Fig. 2 is adopted herein. In this convention, a core is representedas an elongated rectangle. A winding linked to a core is represented inthe drawing by a slanted line making an acute angle with the core. Thesense of the winding is represented by the direction of the acute angle,as viewed in the drawing. An acute angle to the left represents a P(positive) sense winding and an acute angle to the right represents an N(negative) sense winding. A multi-turn winding is represented by anumber of such lines. The vertical line connecting one or more of theslanted lines represents the serial connection of the winding to form acoil. For example, the bias coil 17 is connected in series aiding relg.lation to the bias winding '7' of the core 3 and to the bias winding 7of the core 5.

A similar core pair and the operation thereof is described in detail inthe copending application, Serial No. 339,861, entitled MagneticSwitching Device, filed by Jan A. Rajchman on March 2, 1953. The aboveswitching device is employed as a means for switching modulated A. C.signals from a modulated signal source to a desired one out of 11channel outputs in accordance with a combinatorial code applied to theselecting windings.

In Fig. 3, there is shown an illustrative arrangement of twenty-five ofthe core pairs 1 arranged to form a combinatorial switch 30 according tothe present invention. Both terminals of the bias coil 17 are connectedto a conventional D. C. current source 31, for example, a battery and aseries connected resistance. Both terminals of the drive coil 23 areconnected to a balanced pulse drive source 33 which may be any source,for example, a blocking oscillator circuit arranged to furnish abalanced pulse having a first phase of one polarity and a second phaseof the opposite polarity. A first set of five difiercnt selecting coils19 and a second set of five different selecting coils 21 are provided.Each of the coils of the first set of selecting coils 19 is connected tothe selecting windings 9 of a different group of five of the corepairs 1. Each coil of the second set of selecting coils 21 is linked tothe selecting windings 21 of a corresponding core pair 1 in each groupof five core pairs 1. One terminal of each of the individual selectingcoils 19 and 21 is connected to a common ground indicated in the drawingby the conventional ground symbol. The other terminal of each of theselecting coils 19 of the first set is connected to a different one of aset of five switches which may, for example, be the triode tubes 37through 41. The other terminal of each of the selecting coils 21 of thesecond set is connected to a different one of another set of switches,for example, the five triode tubes 42 through 46. A different outputcoil 25 is provided for each core pair 1.

The operation of the switch 30 is explained in connection with therepresentative hysteresis loop 50 of Fig. 4 and the waveforms 6i) and 61of Fig. 5. The hysteresis loop 50 is the operating loop of any core ofthe switch cores 3 and 5 of a core pair 1, and conveniently, may be themajor loop for the magnetic material, A D. C. bias is applied to each ofthe cores of the switch by applying a suitable current to the bias coil17. The amplitude of the bias current is sulficient to magnetize each ofthe cores to a zero induction condition as represented by the point 52of the hysteresis loop 59. Each of the tubes in both sets of selectingvacuum tubes is conducting and a current is flowing in each of theselecting coils 19 and 21. The ampitude of the selecting currents isregulated such that each core is excited to the negative direction ofsaturation as represented by the point 54 of the loop 50. The amplitudeof both the D. C. bias current and the selecting currents is determinedfrom the particular hysteresis loop of the material, and, in general,depends upon the previous history of a core. In the present embodiment,however, the largest operating loop for each of the cores is the majorloop and is determined by the largest value of the respective drive andselecting currents used. Consequently, the value of the D. C. biascurrent required for bringing a core to a zero induction condition iswell determined.

A particular one of the core pairs 1 is selected by rendering one of theselecting triodes in the first set and one of the selecting triodes inthe second set non-conducting. For example, the topmost core pair 1 maybe selected by rendering the triodes 37 and 42 non-conducting, as byapplying a negative pulse to each control grid. The cores 3 and 5 of thetopmost core pair 1 are, therefore, returned to the zero inductioncondition by the D. C. bias current. The remaining cores in the topquintet partially return towards the zero induction condition to thestate represented by the point 56 of the loop 50 due to the mode 37being rendered non-conducting. Because the magnetic material is notperfectly rectangular, a flux change A4: occurs in each'core of thesefour core pairs. A flux change A also occurs in each core linked by theselecting winding 21 which is connected to the triode 42. The fluxchange A induces a disturbing voltage in the respective output windings15 of the cores 3 and of these half-selected core pairs. However,because of the series opposition connection of the respective outputcoils 25, these voltages cancel. Also, the selected core pair 1 hasequal and opposite disturbing voltages induced in its output windings 15when the state of the cores 3 and 5 is returned to the zero inductioncondition. These voltages likewise cancel each other in the output coil25 of the selected core pair 1.

' Observe that the selection of a desired core pair is a pure digitalone because the amplitude of the pulse applied to the selecting triodetube in each set does not determine the state of the selected cores 3and 5 as was the case in certain prior magnetic switches. Instead, thestate of the selected core is determined by a single D. C. current whichcan be closely regulated. This is particularly advantageous in digitalmachines because the amplitude of the selecting pulses need not beclosely regulated and a consequent saving in equipment can be obtained.The waveform 60 of Fig. 5 illustrates the current flow in each of thetwo selecting coils 19 and 21 which current decays exponentially fromits initial amplitude I to a substantially zero amplitude in a time t1.7 i

Assume, now, that after the time t1, the balanced drive pulse 62 of thewaveform 61 is applied to the drive coil 23 by the balanced pulsegenerator 33. The balanced pulse 62 comprises a first, positive phase 63and a second, negative phase 64. The first positive phase excites thecore 3 of the selected core pair 1 from the zero induction conditiontowards the positive direction of saturation along the one branch of thehysteresis loop 50 (Fig. 4), to a state represented by the point 57.Similarly, the first, positive phase 63 drives the core 5 of theselected core pair 1 across to the other branch, as indicated by thedotted line and towards the negative direction of saturation along thisother branch to a state represented by the point 59. The two voltagesrespectively induced in the output windings 15 of the cores 3 and 5 areadditive in the output coil 25 of the selected core pair. The core 3 ofthe remaining half-selected core pairs 1' is excited by the first,positive phase 63 of the balanced drive pulse 62 from the point 56toward a positive direction of saturation along the bottom, fiat portionof the hysteresis loop 50, and similarly, the core 5 of each of thehalfselected core pairs 1 is excited from the point 56 into furthersaturation in the N direction. Because the magnetic excursion of eachcore 3 and 5 of the respective half-selected core pair 1 is in adifferent direction from the point 56, there may be slight voltagesinduced in the respective output windings 15 of a core pair because ofthe imperfect saturation condition of the materials used. Thesedisturbing voltages are additive in the respective output coils 25. Theamplitude of the net disturbing voltage appearing in any one output coil25 of a halfselected core pair depends on the slope of the lower portionof the hysteresis characteristic in the neighborhood of the point 56.Thus, it is desirable to select a material for which the ratios of theslopes at saturation (points 56 and 54) to the maximum slope (point 52)are as small as possible in order to maximize the discrimination betweenthe desired output voltage and the disturbing voltage. v

The eifective ratio of the slopes between the unselected position (point52) of a core pair may be increased by employing the system described inthe above-mentioned application, Serial No. 339,861. Briefly, thissystem comprises a quartet of cores in each switch position instead of acore pair. The additional core pair is connected in the same manner asthe individual core pairs described above except that the coresare'biased to the P direction of saturation. The output coils of each ofthe pairs of a quartet are connected to form another diflerent outputcoil. Also, one pair of the quartet may be comprised of a magneticmaterial having a linear hysteresis characteristic.

. The second, negative phase 64 of the balanced drive pulse 62 (Fig. 5)returns the cores 3 and 5 of the selected pair back to substantially thezero induction condition as represented by the point 52 of the loop 50.A relatively large, output voltage opposite to the polarity of the firstoutput voltage is induced in the output coil 25 of the selected corepair 1. Likewise, a very small, or no disturbing voltages are induced inthe output coils 25 of each half-selected core pair 1.

The advantage derived from thus employing the selecting and drivecurrents is that the selecting current source is required to supply onlythe magnetizing current required to change the cores 3 and 5 of a corepair from the low permeability region at the point 56 to the highpermeability region at the point 52. Therefore, in practice, the meansfor furnishing the various selecting currents may be low power leveldevices, for example, transistors. In the case of metallic cores, eddycurrents flow and a different time from the period t1 of Fig. 4 may berequired for the cores 3 and 5 of the selected core pair to settle tothe zero induction condition because of the opposing effects of the eddycurrents. The period t1 can be shortened either by applying a small,positive overshoot to the selecting coils or by applying a smallamplitude, positive pulse to the D. C. bias coil during the selectiontimev interval. In systems employing cores of ferrite or ferrospinelmaterial, there are substantially no eddy currents, and therefore, thetime interval required for a coreto settle to the zero inductioncondition is extremely short.

In Fig. 6, the memory system 70 is comprised of an array 72 of 10,000memory cores arranged in 100 rows and .100 columns. The array 70 may bea double-coincident magnetic array and may be similar to that describedin the above-mentioned article by Jan A. Rajchman entitled A myriabitmagnetic matrix memory. Thus, each memory core is linked by adifferentone of the row windings 74, by a different one of the columnwindings 76 and by a sensing winding 78. Each row winding 74 isconnected to one output of a row switch 80. The row switch is comprisedof a 25x4 array of the core pairs 1. Each column winding 76 is connected .to a different one of the outputs of a column switch 82. The rowswitch 80 and the column switch 82 are similar. Therefore, only thearrangement of the row switch 80 is described. The row switch 80 hasfour different quadrants. Each quadrant is set out by a circle 86 andcontains a group of twenty-five of the core pairs 1. Five difierentcolumn selecting coils 88 through 392 and five different row selectingcoils 94 through 98 are provided. Each intersection of a row and columncoil in the top two and the bottom two of the quadrants 86 represent acore pair.

The core pair 1 at the intersection encircled by the dotted line 100 isshown in detail in Fig. 7 and comprises a core 3 and a core 5. In Fig.7, the selecting row coil 96 and the selecting column coil 87 of the rowswitch 80 are connected in series aiding relation to the respectiveselecting windings 9 and 11 of the cores 3 and 5. The D. C. bias coil 17(not shown in detail in the switch 80 of Fig. 6) is connected in seriesaiding relation to the respective bias windings 7 of the cores 3 and 5and operates to bias every core pair 1 of the switch 80 to the zeroinduction condition as explained previously. The output windings 17 ofthe cores 3 and 5 are connected in series opposition to form the outputcoil 85.

Referring again to Fig. 6, the row coil 88 is connected to the rowwinding of each core 3 and 5 of five diiferent core pairs 1 in each ofthe four quadrants, and is then connected to acomrnon terminal 81,indicated by the conventional ground symbol. Likewise, each of the rowcoils 89 through 92 are connected in series aiding rela tion to theselecting windings of five of the core pairs in each quadrant, and eachof these five coils is also connected to the common terminal 81. Eachcolumn coil 94 through 98 is connected in combinatorial fashion to fivedifferent ones of the core pairs in each of the quadrants, and is thenconnected to a common terminal 83, indicated by the conventional ground.There is an individual output coil 85 for each core pair. One terminalof each of the output coils 85 is connected to the common ground. Theother terminal of each output coil 85 is connected to a respective oneof the row windings 74 of the memory array 72.

An individual one of the four drive coils 101 through 104 is connectedin series opposition to the drive windings 13 of each of the core pairs1 in one of the quadrants. A particular one of the drive coils 101through 104 is selected by the 2 X 2 matrix 105 which is illustrated bytwo vertical lines intersecting two other horizontal lines to form fourdifferent intersections 107. Each of the intersections 107 may becomprised of a core pair 1. The vertical columns and the horizontal rowsof the matrices 105 are each connected to one of two different selectingmeans (sel.) 103 which operate to select one core pair in accordancewith two different binary inputs. Each of the core pairs 1 representedby the intersection 107 has a drive coil 109 connecting the drivewindings of the two cores of each pair in series opposition. The drivecoil 109 is connected to the output of the balanced pulse generator 33.The drive coil 109 is also connected in parallel with a similar 2 X 2array 105 of the core pairs 1 which array is used to drive the selectedcore pair 1 in a selected one of the quadrants of the column switch 82.

The operation of the memory system 70 may be as follows: Assume that itis desired to write a binary one, represented by the state P, in adesired one of the memory cores of the array 72. One row winding 74 andone column winding 76 intersect in the desired memory core. The row andcolumn address of the desired memory core is furnished in two steps byauxiliary equipment, which may be, for example, a digital computer. Thefirst step comprises priming one core pair in each quadrant of the rowswitch 80 and the column switch 82. This priming is preferablysimultaneous in order to reduce the access time. A core pair in eachquadrant is selected by removing the current from the one row selectingcoil and the one column selecting coil which are respectively connectedto the selected windings 9 and 11 of the one row core pair in each ofthe quadrants 86. The second step comprises selecting one of thequadrants by applying the binary address of the desired quadrant to theselecting means 108 of the 2 X 2 arrays 105 thereby priming a core pair107 in each of the 2 X 2 arrays. row and column switches are primed, adrive pulse 110 is applied by the balanced pulse generator 33 to all thecore pairs of both the 2 X 2 arrays 105. The selected core pair in eacharray 105 furnishes a balanced drive pulse, substantially the same asthe drive pulse 110, on its output coil. This drive pulse is applied byone array 105 to all the core pairs 1 of one quadrant 86 of the rowswitch 80 and by the other array 105 to all the core pairs 1 of onequadrant 86 of the column switch 82. The primed core pair in theselected quadrants furnish a balanced drive pulse similar to the pulse62 of Fig. to the one row winding '74 and the one column winding 76which intersect in the desired memory core. The coincidence of the firstphase 63 of the drive pulses 62 in the desired memory core generatessufficient magnetizing force to excite it to the state P and thecoincidence of the negative phase of the drive pulses 62 generatessuficient magnetizing force to return the memory core back to the stateN. Therefore, the desired memory core of the array 72 is first driven tothe state P and then to the state N. At the end After the core pairs ofthe of the balanced pulses 62, the desired memory core is at the state Nregardless of its initial state of magnetization. All disturbingcurrents produced by the half-selected core pairs 1 are of substantiallyzero amplitude. There are substantially no secondary currents flowing inthe excited row coil 74 and the column coil 76 at the termination of thedrive pulse 62. Therefore, the row and column switches need not be leftfor a predetermined time in order to allow the magnetic energy stored inthe inductance of the driven core pair to dissipate across a highresistance as is the case when a single polarity, unbalanced drive pulseis employed. One manner of viewing the effect of the balanced pulse isto consider that the flow of current in a pure inductance is completelystopped by applying a voltage tending to produce an equal current of theopposite polarity through the inductance thereby cancelling thepreviously fiowing circuit and, consequently, the stored energy.Accordingly, one advantage of using a balanced system is that the timeinterval of the drive pulse need be only of a duration necessary to turnover the selected memory core, and no longer. When the memory cores arecomprised of appropriate ferrite or ferro-spinel materials, thisturn-over time is extremely short and may be in the order of /3 of amicrosecond or less, when information is written into a memory core bymeans of the core pairs and the balanced drive.

The balanced system of the present invention permits the employment ofeither a balanced PN drive pulse or a balanced NP drive pulse. Thus, thewriting of a binary one or a binary zero into a desired memory core issimplified. For example, when it is desired to write a binary zero, thedrive pulse is comprised of a first positive phase followed by a secondnegative phase. When it is desired to write a binary one, the drivepulse is comprised of a first negative phase followed by a secondpositive phase. The last phase of the drive pulse determines the writteninformation. The prior switching systems generally employed a drivewhich is of a single order of polarity, for example, a first P pulse,and subsequently, a second N pulse. Thus, in certain prior systems, theinterrogation of a desired memory core was carried out by employing afirst pulse of a given polarity, which, in practice, always preceded arestoration employing a pulse of the opposite polarity.

Information may be read out of the memory array 72 by operating the rowswitch 80 and the column switch 82 thereby applying a balanced drivepulse which has one order of polarity, for example, PN from each switch.The output voltage induced in the output winding 78 during the firstphase of the drive pulses is observed. For example, if a binary zero wasoriginally stored in the interrogated memory core, the first positivephase of the driving pulses reverses the state of this memory core tothe state P and the second, negative phase returns the memory core backto the state N. Therefore, the output pulses of the waveform 111 areinduced in the output winding 78. If the interrogated memory core is inthe state P, there will be substantially no output voltage during thefirst positive phase of the drive pulse, and a relatively large outputvoltage during the second negative phase of the drive pulse. Thus, theinformation stored in a memory core can be ascertained by observing theamplitude of the voltage induced in the output winding 78 during thefirst positive phase of the drive pulses.

' Alternatively, the output voltage induced in the sensing winding 78may be integrated during the entire time interval of the driving pulses.The resulting amplitude of the integrated voltage output then indicateswhat the initial state was of the selected memory core in a mannerproviding a high signal-to-noise ratio. A system employing integrationof the output voltage induced in an output winding during a PN cycle isdescribed in an application, Serial No. 353,8l7 entitled Magnetic MemorySystem, filed by Ian A. Rajchman et al., on May 8, 1953.

In the memory system of Fig. 6, the information readout of the selectedmemory core can be restored by selectively following the first PNbalanced drive pulse by a balanced NP drive pulse. The voltage inducedin the output coil 78 determines whether or not the PN drive is followedby the NP drive. Thus, referring to the waveforms 61 and 111 of Fig. 5,when the selected memory core was initially in the state N, the NP driveis not applied as indicated by the dotted lines. However, when theselected memory core was initially in the state P, the NP drive 112 isapplied. The'initial selection is carried out in the time 2 during whichthe two core pairs of the respective matrix switches are selected. Acomplete access cycle is carried out in the time t2 and includes theadditional time for applying the balanced drive pulses used forinterrogation and restoration. During any one access cycle t2, theselecting currents of the last selected core pair of the row and thecolumn switches are allowed to increase to a normal inhibit amplitude Iand, but not necessarily, the selecting currents of the core pairs atanother memoryposition are allowed to decay from a value I to a Zerovalue, as illustrated by the respective waveforms 60 and 113 ofFig. 5.There is no upper limit to the time required for the initial selection,the longer the time n, the smaller the voltage drop across a selectingcoil and, therefore, a consequent reduction in the power required for aselection. A short, dead time D may be employed intermediate the PN andthe NP balanced pulses in order to allow for proper operation of thelogical gates of the auxiliary equipment.

In Fig. 8, there is shown a memory system 120 having a capacity of 256words each having sixteen binary digits. For convenience of drawing, thesixteen memory planes M1 through M16 are shown in two dimensions. Eachof the memory planes comprises a rectangular array having 256 columnsand sixteen rows. A respective binary digit of a word is stored in acorresponding position in each of the memory planes. T we hundred andfifty-six different row coils 122 are provided. Each row coil is linkedto a corresponding row of memory cores in each of the memory planes. Therow coils 122 are terminated'at the memory end of the system in a commonconductor 124. Each of the row coils is connected in series oppositionto the output windings of a respective one of the 256 core pairs ofarowswitch 126. The other end of each row coil 122 is terminated at theswitch end of the system in a common conductor 128. The row switch 126may conveniently be arranged in four different quadrants each having 64core pairs. Each core pair is provided with four different selectingwindings. The four selecting windings of the respective core pairs ineach quadrant are connected in combinatorial fashion to form sixteen rowcoils 127 for selecting one core pair in each quadrant, i. e. the rowwindings of alternate halves, quarters, eights, and

sixteenths of the core pairs are connected to a different one of the rowcoils 127. Each of the sixteendiiferent selecting coils 127 of the rowswitch 126 are connected to a respective one of the outputs of sixteenrow-select amplifiers 130. v I

Each column of memory cores of each memory plane M1-M16 is linked by arespective one of sixteen different column coils 132. Sixteen differentcolumn switches 134 are provided. Each column switch 134 has sixteendifferent core pairs and may be divided into four different quadrants,each quadrant having four different ones of the core pairs. Fourdifferent selecting coils 136 are provided. Each two of the selectingcoils 136 are connected in combinatorial fashion to two different onesof the selecting windings of the four core pairs in each quadrant. Eachof the selecting coils 136 is connected to a respective one of theoutputs of four different column-select amplifiers 138. Every memorycore in a respective one of the memory planes is linked by a sens ingwinding 140. 'Each of the sensing windings 140 is connected to autilization device 142 by means of a differcut one of the conductors144, and to one of the inputs of a restore circuitry 146 by means of adifferent one of the conductors 148. The utilization device 142 may beany device responsive to a voltage induced in a sensing winding 140 whena memory core is driven from one direction of saturation to the other.The restore circuitry 146 comprises an assemblage of gates andflip-flops which is responsive to a voltage induced in a sensing windingby a driven core to pass the subsequent balanced drive pulse forrestoring the information read out of the selected memory core.

A logic control unit 150 is provided. This circuit may be any devicearranged for furnishing the address of the desired word and the pulseprogram required for reading or writing information into the desiredmemory address. The four different binary digits used for selecting onecore pair in each of the quadrants of the row switch 126 are supplied bythe logic control unit 150 as electrical signals on four different onesof the sixteen leads of 'a trunk line 152. I

A row driver switch 154 comprising a 2x2 array of four different corepairs is provided. The output windings of a respective one of these corepairs is connected to the drive windings of every core pair in one ofthe four quadrants of the row switch 126. A particular one of the fourcore pairs of the row driver switch 154 is selected by means of twobinary inputs which are connected to four different outputs of the logiccontrol unit 150 by means of four leads of the trunk line 161. Each ofthe column switches 134 has associated therewith a similar column driverswitch 156 for selecting the core pairs in a respective one of the fourquadrants of each of the column switches 134. A particular core pair ineach quadrant of every column switch 134 is selected by the combinationof signals applied by the logic control unit 151) on two different onesof the four leads of a trunk line 158. The four leads of the trunk line153 are connected to the input of a respective one of four differentcolumn selecting amplifiers 138. A particular one of the core pairs ofeach of the column driver switches 134 is selected by means of twodifferent binary inputs which are connected to four different outputs ofthe logic control unit 150 by means of a trunk line 162. An output ofthe logic control unit 150 which furnishes the balanced drive pulse isconnected via the conductor 163 to the row driver switch 154. A set ofoutputs of the logic control unit which selectively furnish a balanceddrive pulse is connected via the trunk line 164 to each individual oneof the column driver switches 156. A D. C. source 160 is connected tothe row switch 126, the row driver switch 154, each column switch 134and each column driver 156. The D. C. bias is arranged for providingsufficient magnetizing force to bias every core of every one of the corepairs to its zero induction condition.

The operation of the memory system may be as follows: Each of the nowselecting amplifiers and the column selecting amplifiers 138 excites therespective cores of each core pair of the row and column switches to theone direction of saturation. Assume, now, that it is desired to write abinary word into the memory position represented by the memory corelocated at the intersection of the first row and the first column ineach of the memory planes. For convenience of description, the operationwill be discussed in connection with the first memory plane M1 onlybecause a similar operation takes place in each of the remaining memoryplanes.

The desired memory core in the plane M1 is intersected by the row coil122' and the colurnn coil 132'. The first part of the address of the rowcoil 122 is furnished by the logic control unit as a combination ofvoltage levels on four of the leads of the trunk line 152, therebyrendering four different ones of the row-selecting amplifiers 130non-conducting. Thus, the voltage applied by these four amplifiers isremoved from the four selecting windings of one core pair in eachquadrant. This one core pair is then brought to the zeroinductioncondition by the D. C. bias. Similarly, the first part of address of the.column coil 132', comprising voltage levels, is furnished by the logiccontrol unit 150 on two different ones of the four leads of the trunkline 158 thereby rendering two of the column-selecting amplifiers 138non-conducting. The output current from these two amplifiers is removedfrom the two selecting windings of one core pair in each quadrant ofeach column switch 134. Therefore, each of these core pairs is primed bybeing brought to the zero induction condition by the D. C. bias. Thesecond part of the address of the row coil 22 is furnished by the logiccontrol unit 150 as, for example, by a combination of voltage levels, tothe row driver switch 154 thereby causing one of its core pairs to bebrought to the zero induction condition by the D. C. bias. Likewise, thesecond part of the address of the colunm coil 132 is furnished by thelogic control unit 150 to the column driver switch 156 thereby primingthe two cores of one of its core pairs.

The logic control unit 150 then furnishes one fullamplitude, balanceddrive pulse comprising a first positive phase and a second negativephase to the row driver switch 154 via the conductor 163. Anotherhalf-amplitude, balanced drive pulse whose phases are opposite to thoseof the row driver pulse is furnished to the column driver switch 156associated with the plane M1 via one lead of the trunk line 164. Thisone drive pulse is passed by the one primed core pair of the row driverswitch 154 to each core pair of one quadrant of the row switch 126. Theother balanced drive pulse is passed by the primed core pair of thecolumn driver switch to each of the core pairs of one quadrant of thecolumn switch 134 associated with the plane M1. The full-amplitude,balanced drive pulse from the row driver switch 154 causes a flux changein the core pair linked by the row coil 122' and the half-amplitudedrive pulse from the column driver switch causes an opposite fiux changein the core pair linked by the column coil 132'. The net magnetizingforce generated by these two drive pulses in the selected memory core isinsufficient to turn over the memory core. Upon the termination of thesedrive pulses, the logic control unit 150 furnishes a second,full-amplitude balanced drive pulse comprising a first negative phaseand a second positive phase to the row driver switch 154. This drivepulse is passed by the prime core pair of the row driver switch and oneprimed core pair of the row switch 126 to the row coil 122. Nohalf-amplitude drive pulse is applied to the column switch 134 which isassociated with the memory plane M1 The second balanced drive pulse onthe row coil 122' generates sufiicient magnetizing force to excite thedesired memory core in the memory plane M1 first to the state N, andthen to the state P. Therefore, a binary one is stored in this core.

The logic control unit 150 does or does not furnish a half-amplitude,balanced drive pulse to the respective column switches 134 in accordancewith the binary digits in the word position. Thus, if a binary zero isin the word position corresponding to a memory plane, a halfamplitude,balanced drive pulse is applied to the associated column switch duringthe time interval of the second full-amplitude, balanced pulse on therow coil 122'. If a binary one is in the word position corresponding toa memory plane, a half-amplitude, balanced drive pulse is applied to theassociated column switch during the time interval of the firstfull-amplitude, balanced pulse on the row coil 122.

Information may be read out of any desired memory core by applyingsimilar, first and second full-amplitude balanced drive pulses to therow switch 126, and observing the voltage induced in the respectivesensing windings 140. Thus, if an interrogated memory core is storing abinary one, represented by the state P, substantially no change in itssaturation condition is produced during the first positive phase.Consequently, substantially no Voltage is induced in the coupled sensingwinding during the first phase, thereby indicating that a binary one isstored in the interrogated memory core. If, however, the interrogatedmemory core is storing a binary zero, represented by the state N, thefirst phase of the fullamplitude drive pulse produces sufiicientmagnetizing force to drive it to the state P. Consequently, a relativelyhigh voltage is induced in the coupled sensing winding 140 during thefirst positive phase.

In the case of a binary zero, the negative phase of the drive pulsereturns the interrogated memory core to the state N and the informationstored in the memory core is not destroyed. However, in the case of abinary one, the neagative phase of the full-amplitude pulse brings theinterrogated memory core to the state N and the information isdestroyed. The information can be written back into or restored in theinterrogated memory core by means of the restore circuitry 146. Forexample, when a binary zero is read out, the relatively high voltageinduced in the sensing winding 140 during the first phase of thefull-amplitude drive pulse is used to prime a gate. There is a separategate for each memory plane M1-M16 in the restore circuitry 146. Ahalf-amplitude balanced pulse comprising a first, positive phase and asecond, negative phase is applied to the restore circuitry 147 by thelogic control unit 150 via the conductor 165. The half-amplitudebalanced drive pulse then is passed through the primed gate of therestore circuitry 146 and is applied to the column drive switch 156 ofthe associated memory plane via a c0nductor 167 during the time intervalof the second, fullamplitude drive pulse from the row switch 126.Therefore, the half-amplitude, drive pulse inhibits the drive pulse fromthe row switch '126 from changing the state of the interrogated core.When a binary one is read out, the relatively low voltage induced in thecoupled sensing winding 140 does not prime the gate of the restorecircuitry 147. Therefore, the half-amplitude, drive pulse is not passedand the second, full-amplitude pulse from the row switch 126 succeeds inrestoring the binary one in the interrogated memory core.

There has been described herein an improved magnetic switching systemwhich furnishes a balanced output pulse on a selected one of a pluralityof output coils. There has also been described arrangements of aplurality of switches according to the invention in magnetic memorysystems for providing improved access time and simplified methods ofwriting information into and reading information out of such systems.

What is claimed is:

1. A switching system comprising a plurality of magnetic core pairs,each core of said core pairs comprising a magnetic materialcharacterized by having a substantially rectangular hysteresis loop,means for applying currents to magnetically saturate each core, meansfor applying a bias sufiicient to excite each core to a substantiallyzero induction condition, means for selectively removing said currentsfrom the two cores of one said pair thereby permitting said bias tobring said one pair to a zero induction condition, and means forapplying to every core pair a drive pulse having a first phase of onepolarity and a second phase of the opposite polarity, said drive pulsebeing applied to the respective cores of each said pair in oppositesenses.

2. In a memory system having a plurality of memory cores, each of saidcores comprising a magnetic material characterized by having asubstantially rectangular hysteresis loop, first and second windingslinking different ones of said memory cores, selecting means forselecting desired ones of said memory cores, said selecting meanscomprising means for producing a first drive pulse on one of said firstwindings linking all said desired memory cores, and means for producinga second drive pulse on selected ones of said second windings, eachsecond winding linking at least one of said desired memory cores 13 saidfirst and second drive pulses each having firstand second phases ofopposite polarities.

3. In a memory system in accordance with claim 2 wherein said firstdrive pulse comprises a first fullamplitude phase of one polarity and asecond fullamplitude phase of the opposite polarity and said seconddrive pulse comprises first and second phases each, respectively, ofapproximately one-half the amplitude and of an opposite polarity to saidfirst and second phases of said first drive pulse. t 4. In a memorysystem in accordance with claim 2 wherein said means for producing saidfirst drive pulse includes a magnetic switch having a plurality of corepairs, each core of said core pairs comprising a magnetic materialcharacterized by having a substantially rectangular hysteresis loop,each pair having an output winding coupled to an individual one of saidfirst windings, means for biasing the respective cores of a selected oneof said core pairs substantially to a zero induction condition whileholding the respective cores of said nonselected pairs in asubstantially saturated condition, and means for applying a drive pulseto all said core pairs.

5. In a memory system in accordance with claim 2 wherein said memorycores are arranged in a plurality of rectangular arrays, each arrayhaving rows and columns, means linking a diiferent one of said firstwindings to a corresponding row in each array, and means linking adifferent one of said second windings to every core in a respective oneof said arrays.

6. In a memory system having a plurality of memory cores individuallyidentifiable as corresponding to the elements of an array arranged inrows and columns, a first switch means having a plurality of magneticcore pairs, each pair having an output coil respectively linked to allthe elements corresponding to a row of memory cores, a second switchmeans having a plurality of magnetic core pairs, each pair having anoutput coil respectively linked to all the elements corresponding to acolumn of memory cores, each core of said core pairs of said first andsecond switch means comprising a magnetic material characterized byhaving a substantially rectangular hysteresis loop, means for selectingthe core pair of said first switch means and the core pair of saidsecond switch whose output coils are linked to said desired memory core,bias means for driving each core of said selected core pairssubstantially to a zero induction condition, and drive means forapplying a drive pulse having a first phase of one polarity and a secondphase of the opposite polarity to said first and second switch meansthereby to induce a drive pulse having a first phase of one polarity anda second phase of the opposite polarity in said output coil of saidselected core pair of said first and second switch means and therebyexciting said desired memory core.

7. A memory system as recited in claim 6, each said drive pulsecomprising a first phase of the same one polarity and a second phase ofthe opposite polarity.

8. A magnetic switch comprising a plurality of core pairs, each core ofsaid core pairs comprising a mag netic material characterized by havinga substantially rectangular hysteresis loop, selecting coils linked incombinatorial fashion to groups of said core pairs for selecting onepair in each group, a bias coil linked to every core pair for drivingthe two cores of said selected pairs substantially to a zero inductioncondition, a plurality of drive coils each linked to every core pair inan individual one of said groups, and means for applying a drive pulsehaving a first phase of one polarity and a second phase of the oppositepolarity to a selected one of said drive coils thereby driving the twocores of said selected core pair in one of said groups.

9. A magnetic switch as recited in claim 8, said drive coils beinglinked to the two cores of each core pair in series opposition, andincluding a plurality of output t 14 coils each linked to the two coresof an individual one of said core pairs in series opposition.

10. A magnetic switch as recited in claim 8, each said selecting coilsbeing linked to the two cores of a core pair in series aiding relation.i

11. In a memory system having a plurality of memory cores, each of saidcores comprising a magnetic material characterized by having asubstantially rectangular hysteresis loop, a first and a second windingeach linking a different group of said cores, one of said cores beingcommon to two of said difierentgroups and one or more .of said cores notcommon to said two groups, selecting means for selecting said one core,said selecting means comprising means for producing a first drive pulseon said first Winding and means for producing a second drive pulse onsaid second winding, said first and second drive pulses each havingfirst and second phases of opposite polarities.

12. In a memory system, the combination comprising a magnetic switchhaving pairs of magnetic cores, each of said cores being characterizedby having a substantially rectangular hysteresis loop, said core pairshaving windings wound thereon in a manner tending to cancel disturbingvoltages induced in said windings due to the selection of one of saidcore pairs, means for selecting a desired one of said core pairscomprising means for applying magnetizing forces to all said cores in adirection to drive said cores to a substantially saturated condition,and means for removing said currents from selected ones of said windingslinked to said desired core pair, thereby driving the cores of saidselected pair to a substantially zero induction condition.

13. In a memory system, the combination comprising a magnetic switchhaving pairs of magnetic cores, each of said cores being characterizedby having a substantially rectangular hysteresis loop and each of saidcore pairs having windings wound thereon in a manner tending to canceldisturbing voltages due to the selection of a desired one of said corepairs, and means for selecting said desired core pair comprising meansfor applying currents to said windings to drive said cores to asubstantially saturated condition, and means for removing said currentsfrom selected ones of said windings, thereby driving the cores of saidselected pair to a substantially zero induction condition, and means forapplying a magnetizing force of one polarity to one core of each of saidcore pairs, and a magnetizing force of the opposite polarity to theother core of each of said core pairs.

14. In a memory system having an array of magnetic cores, each of saidcores being of substantially rectangular hysteresis loop material andeach of said cores having drive windings and a sensing winding linkedthereto, the combination comprising means for applying a first drivepulse having a first phase of one polarity and a second phase of theopposite polarity to one of said drive windings of a desired one of saidcores, and means responsive to the voltage induced in said sensingwinding during the first phase of the first drive pulse for selectivelyapplying a second drive pulse whose phases are opposite to those of saidfirst drive pulse to another of said drive windings of said desiredcore.

15. In a magnetic switch having core pairs and windings wound on thecores of said core pairs, each of said cores being of substantiallyrectangular hysteresis loop magnetic material and each of said coreshaving two directions of saturation, the combination comprising meansfor magnetizing each of said cores to one of said directions ofsaturation, means for applying a bias current to each of said cores in adirection to drive a core towards the other of said directions ofsaturation, and means for removing the magnetizing force from a selectedcore pair, said bias current operating to bring each of the cores ofsaid selected core pairs to a substantially zero induction condition,and means for applying a drive pulse having a first phase of onepolarity 15 and a second phase of the opposite polarity to each of saidcores, said drive pulse operating to magnetize the two cores of eachpair towards opposite directions of saturation.

16. In a memory system, the combination comprising a magnetic switchhaving pairs of magnetic cores, each of said cores being characterizedby heaving a substantially rectangular hysteresis loop, means forselecting a desired one of said core pairs comprising means for applyingselecting currents to every core, said selecting current operating todrive each of said cores to one direction of saturation, means forapplying a bias current having an amplitude suflicient to bring each ofsaid cores to a substantially zero induction condition in the absence ofsaid selecting currents, means for removing said select- 15 15 ingcurrents from said selected core pair, and means for applying a drivepulse having alternate phases to each of said cores, thereby causingsaid selected core pair to produce an output pulse having alternatephases.

References Cited in the file of this patent UNITED STATES PATENTS2,666,151 Rajchman Jan. 12, 1954 2,691,152 Stewart-Williams Oct. 5, 19542,691,153 Rajchrnan Oct. 5, 1954 2,691,154 Rajchman Oct. 5, 19542,691,155 Rosenberg Oct. 5, 1954 2,700,155 Clayton Jan. 18, 1955

